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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Document order number MC33982/D Rev 2.0, 10/2002
Preliminary Information Intelligent High Current SelfProtected Silicon High-Side Switch
33982
INTELLIGENT SWITCH
The 33982 is a self-protected silicon 2mOhm high-side switch used to replace electromechanical relays, fuses, and discrete devices in power management applications. The 33982 is designed for harsh environments, and it includes self-recovery features. The device is suitable for loads with high inrush current, as well as motors and all types of resistive and inductive loads. Programming, control, and diagnostics are implemented via the Serial Peripheral Interface (SPI). A dedicated parallel input is available for alternate and Pulse Width Modulation (PWM) control of the output. SPI programmable fault trip thresholds allow the device to be adjusted for optimal performance in the application. The 33982 is packaged in a power enhanced 12 x 12 PQFN package with exposed tabs. Features: * Single 2.0 m Max High-Side Switch with Parallel Input or SPI Control * 6.0 V to 27 V Operating Voltage with Standby Currents < 5.0 A * Output Current Monitoring Output with two SPI Selectable Current Ratios * SPI Control of: Overcurrent Limit, Overcurrent Fault Blanking Time, Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout, slew rates and Fault Status Reporting * SPI Status Reporting of: Overcurrent, Open and Shorted Loads, Over Temperature, Under and Overvoltage Shutdown, Fail-Safe Pin Status, and Program Status. * Enhanced 16 V Reverse Polarity VPWR Protection
FC SUFFIX PLASTIC PACKAGE CASE 1402 PQFN
2 m
ORDERING INFORMATION
Device PC33982FC/R2 Temperature Range (TA) - 40C to +125C Package PQFN
33982 Simplified Application Schematic VCC 33982 VCC WAKE SI SCLK MUX CS SO RST FS IN A/D
FSI OUT LOAD GND PWRGND
VPWR
FB
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 2002
VPWR
VDD
Internal Regulator Programmable Switch Delay 0 - 448 ms
Over Voltage Protection Selectable Slew Rate Gate Drive
CS SCLK SO SI RST WAKE IN FS
SPI 3 MHz LOGIC
OUT
Selectable Current Limit 100 A - 150 A Selectable Current Detect Time 0.125 - 128 ms Open Load Detect Over Temp Detect Selectable Output Current Recopy 1/6000 or 1/4000 Selectable Over Current Dectect 15 A - 50 A
FSI
Programmable Watchdog 512ms - 1024ms
GND
FB
Figure 1. 33982 Internal Block Diagram
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
NC SO VDD SI SCLK CS FSI FS IN RST WAKE CSNS
12 11 10 9 8 13 7 GND 6 5 4 3 2 1
15 14 VPWR
OUT
16
OUT
PIN FUNCTION DESCRIPTION
Pin 1 Pin Name CSNS Description Output Current Monitoring. This pin is used to output a current proportional to the high-side output current and used externally to generate a ground referenced voltage for the microcontroller to monitor output current. WAKE. This pin is used to input a logic [1] signal so as to enable the Watchdog timer function. An internal clamp protects this pin from high damaging voltages when the output is current limited with an external resistor. This input has an internal passive pull-down. Reset. This is an input used to initialize the device configuration and fault registers, as well as place the device in a low current sleep mode. The pin also starts the Watchdog timer when transitioning from logic LOW-to-logic HIGH. This pin should not be allowed to be logic HIGH until VDD is in regulation. This pin has an internal passiv pull down. Serial Input. The Input pin is used to directly control the output. This input has an internal active pulldown and requires CMOS logic levels. This input may be configured via SPI. Fault Status. This is an open drain configured output requiring an external pull-up resistor to VDD for fault reporting. A device fault condition is detected, this pin is active LOW. Specific device diagnostic faults are reported via the SPI SO pin. Fail-Safe Input. The level of this pin determines the state of the output after a Watchdog timeout occurs. This pin incorporates and internal pull-up. If the FSI pin is left to float up to a logic [1] level, the output will turn-ON when in the fail-safe state. When the FSI pin is connected to GND, the Watchdog circuit and failsafe operation are disabled. Chip Select. This is an input pin connected to a chip select output of a system microcontroller. The microcontroller determines which device is addressed (selected) to receive data by pulling the CS pin of the selected device logic LOW, enabling SPI communication with the device. Other unselected devices on the serial link having their CS pins pulled-up logic HIGH disregard the SPI communication data sent. Serial Clock. This is an input pin connected to the master microcontroller providing the required bit shift clock for SPI communication. It transitions one time per bit transferred at an operating frequency, fSPI, defined by the communication interface. See the SPI Interface Characteristics table. The 50 percent duty cycle CMOS level serial clock signal is idle between command transfers. The signal is used to shift data into and out-of the device. See operational description of SPI. Serial Input. This is a command data input pin connected to the SPI Serial Data Output of the master microcontroller or to the SO pin of the previous device of a daisy chain of devices. The input requires CMOS logic level signals and incorporates an internal active pull-down. Device control is facilitated by the input's receiving the MSB first of a serial 8-bit control command. The master ensures data is available upon the falling edge of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit command into the internal command shift register.
2
WAKE
3
RST
4 5
IN FS
6
FSI
7
CS
8
SCLK
9
SI
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 3
PIN FUNCTION DESCRIPTION
Pin 10 Pin Name VDD Description Digital Drain Voltage (Power). This is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost, an internal supply provides power to a portion of the logic, ensuring limited functionality of the device. Serial Output. This is an output pin connected to the SPI Serial Data Input pin of the master microcontroller or to the SI pin of the next device of a daisy chain of devices. This output will remain tristated (high impedance OFF condition) so long as the CS pin of the device is logic HIGH. SO is only active when the CS pin of the device is asserted logic LOW. The generated SO output signals are CMOS logic levels. SO output data is available on the falling edge of SCLK and transitions immediately on the rising edge of SCLK. Serial output data provides status information for each bit assigned following an MSB first-in-first-out protocol when the device is addressed. Fault bit assignments for return data follow OD7 through OD0 are output status bits for message bits 7 through 0. See SPI operational details, command verification, and daisy chain operation. No Connect. No internal connection to this pin. Ground. This pin is the ground for the logic and analog circuitry of the device. Positive Power Supply. This pin connects to the positive power supply and is the source input of operational power for the device. The VPWR pin is a backside surface mount tab of the package. Output. Protected high-side power output to the load. All pins of output have to be connected in parallel for operation according to this specification.
11
SO
12 13 14
NC GND
VPWR
OUT
15 and 16
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
MAXIMUM RATINGS All voltages are with respect to ground unless otherwise noted.
Rating Operating Voltage Range Steady-State VPWR(SS) VIN, RST, FSI ICL(WAKE) IOUTt ECL TSTG TJ -16 to 41 Symbol Value Unit V
Input Voltage (Note 1) WAKE Input Clamp Current Output Current (Note 2) Output Clamp Energy (Note 3) Storage Temperature Operating Junction Temperature Junction to Case Thermal Resistance Junction to Ambient Thermal Resistance ESD Voltage Human Body Model (Note 4) Machine Model (Note 5)
-0.3 to 7.0 2.5 60 TBD -55 to 150 -40 to 150 <1.0 --
V mA A J
C C
C/W C/W V
JC JA
VESD1 VESD2
2000 200
Notes: 1. Exceeding voltage limits on RST, IN, or FSI pins may cause a malfunction or permanent damage to the device. 2. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current using package thermal resistance is required . 3. Active clamp energy using single pulse method. 4. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP - 1500 ). 5.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP - 0 ) and in accordance with the system module specification with a capacitor > 0.01 F connected form OUT to GND.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 5
STATIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Power Input
Characteristic Operating Voltage Range Full Operational VPWR Operating Supply Current (Measured as GND current, IOUT = 0) Operating Supply Current (Measured as GND current, IOUT = 0) Output OFF, Open Load Detect Disabled, WAKE > 0.7 VDD, RST = VLOGIC HIGH Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V) IPWR(sleep) IPWR(on) IPWR(sby) -- -- 5.0 Symbol VPWR 6.0 -- -- -- 27 20 mA mA Min Typ Max Unit V
A -- -- -- -- 10 50 2.0 5.0 28 0.2 5.0 -- 32 0.8 5.5 -- 36 1.5 6.0 5.0 mA A V V V V
TJ= 25 C TJ = 85 C
VDD Supply Current VDD Sleep State Current Over Voltage Shutdown Over Voltage Shutdown Hysteresis Under Voltage Output Shutdown (Note 6) Under Voltage Power-ON Reset IDD(on) IDD(sleep)
VPWR(on) VPWR(ouhys)
VP(uv) VP(und)
Notes: 6. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not go below the under voltage power-on reset threshold.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Output
Characteristic Output Drain-to-Source ON Resistance Symbol RDS(on)25 -- -- -- RDS(on)150 -- -- -- RSD(on) -- -- -- -- -- 5.1 3.4 3.4 4.0 m -- -- -- 3.0 2.0 2.0 m Min Typ Max Unit m
(IOUT = 30 A, TJ = 25C) VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V
Output Drain-to-Source ON Resistance (IOUT = 30 A, TJ = 150C)
VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V
Output Source-to-Drain ON Resistance (Note 7) (IOUT = 30 A, TJ = 25C) VPWR= -12 V Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V) SOCH = 0 SOCH = 1 Over current Low Detection Levels (SOCL[2:0]) (000) (001) (010) (011) (100) (101) (110) (111) Current Sense Ratio (9.0 V < VPWR < 16 V CSNS < 4.5 V) DICR D2 =0 DICR D2=1 Current Sense Ratio (CSR0) Accuracy Output Current: 10 A 20 A 25 A 30 A 40 A 50 A CSR0 CSR1 IOCL0 IOCL1 IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 IOCH0 IOCH1
A 120 80 150 100 180 120
41 36 32 29 25 20 16 12
50 45 40 35 30 25 20 15
59 54 48 41 35 30 24 18
A
-- --
1/40000 1/6000
-- --
-20 -14 -13 -12 -13 -13
-- -- -- -- -- --
20 14 13 12 13 13
%
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 7
Current Sense Ratio (CSR1) Accuracy Output Current: 10 A 20 A 25 A 30 A 40 A 50 A Maximum Current Sense Clamp Voltage TBD TBD TBD TBD TBD TBD VCL(maxsns) 4.5 IOLDC VOLD(thres) 30 2.0 6.0 -- 3.0 7.0 100 4.0 V -20 TSD TSD(hys) 160 5.0 -- 175 -- -- 190 20 A V -- -- -- -- -- -- TBD TBD TBD TBD TBD TBD V %
ICSNS = 15 mA
Open Load Detect Current (Note 8) Output Fault Detect Threshold Output Programmed OFF Output Negative Clamp Voltage 0.5A < = IOUT < = 2.0 A, Output OFF Over Temperature Shutdown (Output OFF) (Note 10) (TA = 125 C) Over Temperature Shutdown Hysteresis (Note 9)
VCL
C C
Notes: 7. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR. 8. 9. Output OFF Open Load Detect Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. Guaranteed by process monitor. Not production tested.
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
STATIC ELECTRICAL CHARACTERISTICS (continued) Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Control Interface
Characteristic Input Logic High Voltage (Note 10) Input Logic Low Voltage (Note 10) Input Logic Voltage Hysteresis (Note 10) Input Logic Pull-Down Current (CSNS, IN,SI) RST Input Voltage Range SO, FS Tri-State Capacitance (Note 11) Input Logic Pull-Down Resistor (RST) and WAKE Input Capacitance (Note 12) Wake Input Clamp Voltage (ICL(WAKE)<2.5 mA) (Note 13) Wake Input Forward Voltage (ICL(WAKE) = -2.5 mA) SO High State Output Voltage (IOH = 1.0 mA) FS, SO Low State Output Voltage (IOL = -1.6 mA) SO Tri-State Leakage Current (CS > 0.7VDD) Input Logic Pull-Up Current (CSB, FSI, Vin >0.7 VDD) (Note 14) Symbol VIH VIL VIN(hys) IDWN VRST CSO IDWN CIN VCL(WAKE) VF(WAKE) VSOH VSOL ISO(leak) IUP Min 0.7VDD -- 100 5.0 4.5 -- 100 -- 7.0 -2.0 0.8 VDD -- -5.0 5.0 Typ -- -- 350 -- 5.0 -- 200 4.0 -- -- -- 0.2 0 -- Max -- 0.2VDD 750 20 5.5 20 400 12 14 -0.3 -- 0.4 5.0 20 Unit V V mV A V pF k pF V V V V A A
Notes: 10. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN and WAKE input signals. The WAKE and RST signals are derived from an internal supply. 11. Parameter is guaranteed by process monitor but is not production tested. 12. Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitor; but is not production tested. 13. The current must be limited by a series resistance when using voltages > 7.0 V. 14. Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 9
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Power Output Timing
Characteristic Output Rising Slow Slew Rate A (Note 15) (DICR D3=0) Symbol Min Typ Max Unit
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Rising Slow Slew Rate B(Note 17) (DICR D3=0)
SRrA_slow
0.6
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Rising Fast Slew Rate A(Note 15) (DICR D3=1)
SRrB_slow
0.05
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Rising Fast Slew Rate B(Note 16) (DICR D3=1)
SRrA_fast
2.0
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Falling Slow Slew Rate A(Note 15) (DICR D3=0)
SRrB_fast
0.2
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Falling Slow Slew Rate B(Note 16) (DICR D3=0)
SRrA_slow
0.6
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Falling Fast Slew Rate A(Note 15) (DICR D3=1)
SRrB_slow
0.05
V/s
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V SRrA_fast
2.0 V/s
33982 10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
DYNAMIC ELECTRICAL CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted. Power Output Timing
Characteristic Output Falling Fast Slew Rate B(Note 16) (DICR D3=1) Symbol Min Typ Max Unit
6V< VPWR <9V 9V< VPWR <16V 16V< VPWR <27V
Output Turn-ON Delay Time (Note 17) Output Turn-OFF Delay Time (Note 18) Direct Input Switching Frequency Overcurrent Detect Blank (OCTL [1:0]) Time 00 01 10 11 Over Current Hi Detect Blank Time CS to CNS Valid Time Output Switching Delay Time (OSDR [2:0]) tdly(on) tdly(off) fPWM 1.0 20 -- 15 80 300 100 200 -- s s Hz
SRrB_fast
0.2
V/s
tOCL0 tOCL1 tOCL2 tOCL3
tILB CNSVAL
108 6.7 0.84 0.10 1 --
155 9.7 1.2 0.15 10 --
202 12.7 1.6 0.2 20 10 s s ms
000 001 010 011 100 101 110 111
Watchdog timeout (Note 19) (WD[1:0]) 00 01 10 11
tOSD0 tOSD1 tOSD2 tOSD3 tOSD4 tOSD5 tOSD6
44.8 89.6 134.4 179 224 268 313
0 64 128 192 256 320 384 448 83.2 166.4 250 333 416 500 583 ms 496 248 2000 1000 620 310 2500 1250 806 403 3250 1625 ms
tWDTO0 tWDTO1 tWDTO2 tWDTO3
Notes: 15. Rise and Fall Slew Rates A measured across a 5.0 resistive load at HS output = 0.5V to VPWR-3 V. These parameters are guaranteed by process monitoring. 16. Rise and Fall Slow Slew Rates B measured across a 5.0 resistive load at HS output = 0.5V to VPWR-3 V. These parameters are guaranteed by process monitoring. 17. Turn-ON Delay Time measured with the output previous programmed OFF and re-programmed ON from rising edge of CS to 90 percent VOUT with a 5.0 load resistor to ground. 18. 19. Turn-OFF Delay Time measured with output previously programmed ON and re-programmed OFF from rising edge of CS to 10 percent VOUT with a 5.0 load resistor to ground. Watchdog Timeout delay measured from the rising edge of WAKE to RST from a sleep state condition, to output turn-ON with the output driven OFF and SDI floating. The values shown are for WDCR setting of [01]. The accuracy of tWD is consistent for all configured watchdog timeouts.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 11
SPI INTERFACE CHARACTERISTICS Characteristics noted under conditions 4.5 V VDD 5.5 V, 6 V VPWR 27 V, -40C TJ 150C, unless otherwise noted. Typical values noted reflect the approximate parameter mean at TA = 25C under nominal conditions, unless otherwise noted.
Characteristic Recommended Frequency of SPI Operation Required Low State Duration for RST (Note 20) Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 21) Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 21) Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 21) Required High State Duration of SCLK (Required Setup Time) (Note 21) Required Low State Duration of SCLK (Required Setup Time) (Note 21) Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 21) SI to Falling Edge of SCLK (Required Setup Time) (Note 22) Falling Edge of SCLK to SI (Required Setup Time) (Note 22) SO Rise Time (CL = 200 pF) SO Fall Time (CL = 200 pF) SI, CS, SCLK, Incoming Signal Rise Time (Note 22) SI, CS, SCLK, Incoming Signal Fall Time (Note 22) Time from Falling Edge of CS to SO Low Impedance (Note 23) Time from Rising Edge of CS to SO High Impedance (Note 24) Time from Rising Edge of SCLK to SO Data Valid (Note 25) 0.2 VDD < = SO > = 0.8 VDD, CL = 200 pF Notes: 20. 21. 22. 23. 24. 25. RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33982 is the minimum guaranteed time needed from the micro. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1 k on pull-up on CS. Time required for output status data to be terminated at SO. 1 k on pull-up on CS. Time required to obtain valid data out from SO following the rise of SCLK. Symbol Min -- -- -- -- -- 50 Typ -- 50 Max 3.0 167 300 5 167 167 167 -- -- -- -- -- -- -- -- -- -- 50 25 25 25 25 -- -- -- 65 65 167 83 83 50 50 50 50 145 145 105 Unit MHz nS nS S nS ns ns nS nS nS nS nS nS nS nS nS nS
fSPI twrst tCS tENBL tLEAD twSCLKh twSCLKl tLAG tsi (su) tsi (hold) trSO tfSO trSI tfSI tSO(en) tSO(dis) tVALID
CS
VPWR VPWR - 0.5V VPWR - 3V
SRrB
SRfB SRfA
SRrA
0.5V
Tdly(on)
Tdly(off)
Figure 2. Output Slew Rate and Time Delays
33982 12 MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
IOCHx ILOAD Load Current IOCLx tOCH Time tOCLx Figure 3. Over Current Shutdown ILOAD
IOCH0 IOCH1 IOCL0
IOCL1
Load Current
IOCL2 IOCL3 IOCL4 IOCL5 IOCL6 IOCL7 tOCH tOCL3 tOCL2 tOCL1 tOCL0
Time Figure 4. Over Current Low and High Detection
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 13
VIH
RST
tsRST
0.2 VDD
VIL
VIH
CS
0.7 VDD tlead 0.7 VDD 0.2 VDD twSCLKh trSI tlag
VIL VIH
SCLK
tSIsu 0.7 VDD 0.2 VDD
twSCLK tSI(hold) Valid Don't Care tfSI VIL Valid Don't Care VIH
SI
Don't Care
Figure 5. Input Timing Switching Characteristics
Figure 6. Valid Data Delay Time and Valid Time Waveforms
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
SYSTEM APPLICATION INFORMATION
INTRODUCTION
SPI Protocol Description The SPI interface has a full duplex, three wire synchronous data transfer with four I/O lines associated with it: * SI * SO * SCLK * CS The SI/SO pins of the 33982 device follows a first in-first out (D7/D0) protocol with both input and output words transferring the Most Significant Bit (MSB) first. All inputs are compatible with 5.0 V CMOS logic levels. The SPI lines perform the following functions: SCLK--Clocks the internal shift registers of the 33982 device. The Serial Input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO Line Driver on the rising edge of the SCLK signal. It is important the SCLK pin be in a logic Low state whenever CS makes any transition. For this reason, it is recommended the SCLK pin be in a logic[0] whenever the device is not accessed (CS logic [1] state). SCLK has an internal pull-down LDWN . When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). Please see the Data Transfer Timing diagram in Figure 7 and Figure 8.
CSB
SI--This is a serial command data input pin. SI instruction is read on the falling edge of SCLK. An 8-bit stream of serial data is required on the SI pin, starting with D7 to D0. The internal registers of the SPSS are configured and controlled using a 4 bit adressing scheme, as shown in Table 1. Register addressing and configuration are described in Table 1. The SI input has an internal pulldown LDWN. SO--The Serial Output data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CS pin is put into a logic[0] state. The SO data is capable of reporting the status of the output, the device configuration, and the state of the key inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. Fault and Input Status descriptions are provided in Table 11 CS--The Chip Select pin enables communication with the Master device. When this pin is in a logic[0] state, the device is capable of transferring information to and receiving information from the Master. The 33982 device latches-in data from the input shift registers to the addressed registers on the rising edge of CS. The device transfers status information from the power output to the shift register on the falling edge of CS. The SO output driver is enabled when CS is logic [0]. CS should transition from a logic [1] to a logic [0] state only when SCLK is a logic [0]. CS has an internal pull-up, LUP.
SCLK
SI
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
NOTES:
1. 2. 3.
RSTB is in a logic 1 state during the above operation. D0, D1, D2, ..., and D7 relate to the most recent ordered entry of data into the SPSS OD0, OD1, OD2, ..., and OD7 relate to the first 8 bits of ordered fault and status data out of the device.
Figure 7. Single 8-Bit Word SPI Communication
CSB
SCLK
SI
D7
D6
D5
D2
D1
D0
D7*
D6*
D5*
D2*
D1*
D 0*
SO
OD7
OD6
OD5
OD2
OD1
OD0
D7
D6
D5
D2
D1
D0
NOTES:
1 2 3 4
. . . .
R D O O
S T B is in a lo g ic 1 s t a 0 , D 1 , D 2 , ..., a n d D 7 D 0 , O D 1 , O D 2 , ..., a n D 0 , O D 1 , O D 2 , ..., a n
t e d u r in g t h e a b o v e o p e r a t io n . r e la te t o th e m o s t r e c e n t o r d e r e d e n t r y o f d a ta in t o th e S P S S d O D 7 r e la t e t o t h e f ir s t 8 b it s o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e d e v ic e . d O D 7 r e p r e s e n t t h e f ir s t 8 b its o f o r d e r e d f a u lt a n d s t a t u s d a t a o u t o f t h e S P S S
Figure 8. Multiple 8-Bit Word SPI Communication
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 15
The 33982 device is capable of interfacing directly with a microcontroller using an 8-bit SPI protocol. SI Communication SPI communication is accomplished using 8-bit messages. A message is transmitted by the master starting with the MSB D7 and ending with the LSB D0. Each incoming command message on the SI pin can be interpreted using the following bit assignment : the MSB, D7, the watchdog bit (seeTable 1 )and in some cases, a register address bit (seeTable 1). The next three bits, D6-D4, are used to select the command register. The remaining four bits D3-D0 are used to configure and control the output and its protection features.Multiple messages can be transmitted in succession to accomodate those applications where daisy chaining is desirable, or to confirm transmitted data, as long as the messages are all mutliples of 8-bits. Any attempt made to latch in a message that is not 8-bits will be ignored. The SPSS has 8 registers defined (one for internal use), which are used to configure the device and to control the state of the output. The registers are addressed via D6-D4 of the incoming SPI word (seeTable 1 ). Table 1. SI Message Bit Assignment
Bit Sig SI Msg Bit Message Bit Description
SOCHLR, CDTOLR, DICR, OSDR, WDR and NAR registers. See section SO communication * Address x001-- Output Control Register (OCR) allows the master to control the output through the SPI. Incoming message bit D0 reflects the desired states of the high-side output; (IN_SPI); a logic [1] enables the output switch and a logic [0] turns it OFF. A logic [1] on message bit D1 enables the Current Sense (CSNS_EN) pin. Bit D3 must be logic [0] .Bit D7 is used to feed the watchdog, if enabled. * Address x010-- Select Over Current High and Low Register (SOCHLR) allows the Master to configure the output over current low and high detection levels, respectively. In addition to protecting the device, this slow blow fuse emulation feature can be used to optimize the load requirements to match system characteristics. Bits D2-D0 are used to set the over current low detection level to one of eight possible levels are shown in Table 2. Bit D3 is used to set the over current high detection level to one of two levels, outlined in Table 3. Table 2. Over Current Low Detection Levels
SOCLA2 (D2) SOCLA1 (D1) SCOLA0 (D0) Over Current Low Detection
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
50 A 45 A 40 A 35 A 30 A 25 A 20 A 15 A
MSB
D7
Watchdog in: toggled to satisfy watchdog requirements; also used as a Register address bit in some cases. Register Address Bit Register Address Bit Register Address Bit Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content. Used to configure the inputs, outputs, and the device protection features and SO status content.
D6 D5 D4 D3 D2 D1 LSB D0
Table 3. Over Current High Detection Levels
SOCH (D3) Over Current High Detection
0 1
150 A 100 A
Device Register Addressing The nine possible register addresses (D7, D6, D5, D4) and a description of their impact on the device operation are listed below. Also see Table 7. * Address x000-- Status Register (STATR).This register is used to read the device status and the various configuration register contents without disrupting the device operation or the register contents. The register bits D2, D1, D0 determine the content of the first eight bits of SO data. In addition to the device status, this feature provides the ability to read the content of the OCR,
33982 16
* Address x011--Current Detect Time and Open Load Register (CDTOLR) is used by the master to determine the amount of time the device will allow an over current low condition before output latches OFF occurs. Bits D1D0 allow the master to select one of four dead times defined in Table 4. Note that these timeouts apply only to the Over Current Low Detect levels. If the selected Over Current High level is reached, the device will latch off within 20 s. Table 4. Over Current Timing
OCTL[1:0] Over Current Timing
00 01
155 ms 9.7 ms
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Table 4. Over Current Timing
10 11 1.2 ms 150 s 011 100 101 110 111
Table 5. Switching Delay
192 ms 256 ms 320 ms 384 ms 448 ms
A logic [1] on bit D2 disables the Over Current Low (CD dis) Detection timeout feature. A logic [1] on bit D3 disables the Open Load (OL) Detection feature. * Address x100-- Direct Input Control Register (DICR) is used by the master to enable, disable, or configure the direct IN pin control of the output. A logic [0] on bits D1 will enable the output for direct control with the IN pin; a logic [1] on D1 bit will disable the output from direct control. While addressing this register, if the Input was enable for direct control, a logic [1] for the D0 bit will result in a Boolean AND of the IN pin with its corresponding D0 message bit when addressing OCR. Similarly, a logic [0] on the D0 pin will result in a Boolean OR of the IN pin to the corresponding message bits when addressing the OCR. This register is especially useful if several loads are required to be independently PWM controlled. For example, the IN pins of several devices can be configured to operate all of the outputs with one PWM output from the master. If each output is then configured to be Boolean ANDed to its respective IN pin, each output can be individually turned OFF by SPI while controlling all of the outputs, commanded on with the single PWM output. A logic [1] on bit D2 is used to select the high ratio (Iout/ 40000) on the CSNS pin. The default value [0] is used to select the low ratio(Iout/6000). A logic [1] on bit D3 is used to select the high speed slew rate, the default value [0] corresponds to the low speed slew rate. * Address 0101-- Output Switching Delay Register (OSDR) is used to configure the device with a programmable time delay that is active during Output On transitions that are initiated via SPI. Whenever the input is commanded to transition from [0] to [1] via SPI, the output will be held OFF for the time delay configured with the OSDR Register. The programming of the contents of this register have no effect on device failsafe mode operation. The default value of the OSDR register is 000, equating to no delay, since the switching delay time is 0ms. This feature allows the user a way to minimize inrush currents, or surges, when several daisy chained devices are controlled by a common CS , thereby allowing loads to be synchronously switched ON. There are eight selectable output switching delay times that range from 0 to 448ms. * Table 5. Switching Delay
OSDA[2:0] (D2, D1, D0) Timing
* Address 1101-- Watchdog Register (WDR) This register is used by the master to configure the Watchdog timeout. The Watchdog timeout is configured using bits D1 and D0. When D1, D0 bits are programmed for the desired watchdog timeout period, the WDSPI bit should be toggled as well to ensure the new timeout period is programmed at the beginning of a new count sequence.
Table 6. WatchDog Time Out
WDA[1:0] (D1, D0) Timing
00 01 10 11
620 ms 310 ms 2500 ms 1250 ms
* Address x110--No Action Register (NAR). * Address x111--This register is reserved for test and is not accessible with SPI during normal operation. Table 7. SI Address and Configuration Bit Map
2.0 m
D7 D6 D5 D4 STATR OCR SOCHLR SDTOLR DICR OSDR WDR NAR TEST D3 SI Data D2 D1 D0
x x x x x 0 1 x x
0 0 0 0 1 1 1 1 1
0 0 1 1 0 0 0 1 1
0 1 0 1 0 1 1 0 1
SOA3 0 SOCH OL dis FAST SR 0 0 0
SOA2 0
SOA1
SOA0
CSNS EN IN_SPI
SOCLA2 SOCLA1 SOCLA0 CD dis CSNS high OSDA2 0 0 CDT1 IN dis OSDA1 WDA1 0 CDT0 A/O OSDA0 WDA0 0
Motorola Internal Use (Test)
000 001 010
0 ms 64 ms 128 ms
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 17
SO Communication (Device Status Return Data) When the CS pin is pulled low, the output register is loaded and the data is clocked out MSB (OD7) first, as the new message data is clocked into the SI pin. The first eight bits of data that clocks out of the SO, following a CS transition, is dependant upon the previously written SPI word. Bit OD7 reflects the state of the watchdog bit (D7) that was addressed during the prior communication. SO data will represent information ranging from fault status to register contents as chosen by the user by writing to the STATR bits D2,D1,D0 . Note that the SO data will continue to reflect the information that was selected during the most recent STATR write until changed with an updated STATR write.
LSB
Table 8. SO Output Bit Assignment(continued) Device Status Return Format
OD0 This bit reflects the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Fault (FAULT) Status, which is the boolean OR of all of the other fault bits).
* Previous Address 000--If the previous three MSBs are 000, the bits D6-D0 will reflect the current state of the Fault Register (FLTR) Table 9. Fault Register
Any bits clocked out of the SO pin after the first eight will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic 0; this feature is useful for daisy chaining devices as well as message verification. Table 8. SO Output Bit Assignment Device Status Return Format
Bit Sig SO Msg Bit Message Bit Description
D7
D6
D5
D4
D3
D2
D1
D0
x
OTF
OCHF
OCLF
OLF
UVF
OVF
FAULT
D7. Don't Care D6. (OTF) = Over Temperature Flag D5. (OCHF) = Over Current High Flag. (This fault is latched) D4. (OCLF) = Over Current Low Flag. (This fault is latched) D3. (OLF) = Open Load Flag D2. (UVF) = Under Voltage Flag (This fault is latched) D1. (OVF) = Over Voltage Flag D0. (FAULT) = This flag reports a fault and is reset by a read operation
Note: The FS pin reports a fault and is reset by a new Switch ON command (via SPI or direct input IN).
MSB
0D7=0 OD6
Reflects the state of the Watchdog bit from the previously clocked in message. This bit reflects address bit D6 of the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Over temperature Fault (OTF) Status). This bit reflects address bit D5 of the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Over Current Detect Hi Fault (OCHF) Status). This bit reflects address bit D4 of the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Over Current Detect Low Fault (OCLF) Status ). This bit reflects the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Open Load Fault (OLF) Status). This bit reflects the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Under Voltage Fault (UVF) Status). This bit reflects the register contents as selected by the most recent STATR command (e.g., STATR with SOA2,SOA1,SOA0 of 0,0,0 will return the Over Voltage Fault (OVF) Status).
OD5
OD4
OD3
OD2
OD1
* Previous Address 001-- the data in bits OD1 and OD0 will contain respective CSNS_EN and IN_SPI programmed bits. * Previous Address 010-- the data in bits OD3, OD2, OD1, and OD0 contains respectively the programmed Over Current high Detection Level ( see Table 3)and the Overcurrent low Detection level (see Table 2). * Previous Address 011--Data returned in bits OD1 and OD0 are current values for the Over Current Dead Time, illustrated in Table 4. Bit OD2 reports whethe the Over Current Detection timeout feature is active. OD3 reports whether the open load circuitry is active. * Previous Address 100-- The returned data contains the programmed values in the DICR. * Previous Address 101-- D7=0 The returned data contains the programmed values in the OSDR. D7=1 The returned data contains the programmed values in the WDR. * Previous Address 110--OD2 to OD0 Return respectively the state of the IN, FSI and Wake pin (see Table 10)..
Table 10. PIN Register
D2 D1 D0
33982 18
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
IN Pin
FSI Pin
WAKE Pin
* Address 111--Null Data. No previous register Read Back command received, so bits OD2, OD1, and OD0 are null, or 000. The Table 11summarize the SO register content. Table 11. SOBit Map Description
Previous STATR
D7, D2, D1, D0 SO SO SO SO A3 A2 A1 A0 D7 x x x x x 0 1 x x 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 0 1 1
communication following an under-voltage VPWR condition should be ignored. * The RST pin transition from a logic [0] to [1] while the WAKE pin is at logic [0] may result in incorrect data loaded into the status register. The SO data transmitted to the master during the first SPI communication following this condition should be ignored. Watchdog and Fail-Safe Operation If the FSI input is a logic [1], that is, not grounded, the Watchdog timeout detection is active when either the WAKE or RST input pin transitions from logic[0] to [1]. The WAKE input is capable of being pulled up to VPWR with a series of limiting resistance limiting the internal clamp current according to the specification. The Watchdog timeout is a multiple of an internal oscillator and is specified in the Table 6. As long as the WD bit (D7) of an incoming SPI message, is toggled within the minimum watchdog timeout period (WDTO, based on the programmed value of the WDCR register), the device will operate normally. If an internal watchdog timeout occurs before the WD bit, the device will revert to a Fail-Safe mode until the device is reinitialized. During the Fail-Safe mode, the output will be driven ON regardless of the state of the various direct inputs and modes. Failsafe mode can be detected by monitoring the WDTO bit D2 of the WDR register. This bit is logic [1] when the device is in failsafe mode. The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0] or forcing the FSI pin to logic [0]. Table 12 summarizes the various methods for resetting the device from the latched Fail-Safe mode. If the FSI pin is tied to GND, the Watchdog fail-safe operation is disabled. Table 12. Fail-Safe Operation and Transitions to Other 33982 Modes
WAKE RST WDTO OUT Comments
SO Returned Data
D6
D5
D4
D3
OLF 0
D2
UVF 0
D1
OVF CSNS_ EN
D0
Fault IN_SPI
0 WDin OTF OCHF OCLF 1
WDin
0 0 0 1 1 1 1
0 1 1 0 0 0 1
1 0 1 0 1 1 0
0 WDin 1 WDin 0 1 1 0 1
WDin
SOCH SOCLA2 SOCLA1 SOCLA0 OL dis Fast SR 0 0 0 CD dis CSNS high CDT1 IN dis CDT0 A/O
0
1 WDin
OSDA2 OSDA1 OSDA0 WDTO IN pin WDA1 FSI pin WDA0 WAKE pin
General SO Communication statements Any bits clocked out of the SO pin after the first eight will be representative of the initial message bits clocked into the SI pin since the CS pin first transitioned to a logic [0]; this feature is useful for daisy chaining devices as well as message verification. Following a CS transition of [0] to [1], determines if the message was of a valid length and if so, the data is latched into the appropriate registers. A valid message length is a multiple of eight bits. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. The output status register correctly reflects the status of the STATR selected register data at the time that the CS is pulled to a logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following exceptions: * The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid SPI communication never occurred. * Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect data loaded into the status register. The SO data transmitted to the master during the first SPI
0 1 1
0 0 0
x No Yes
OFF OFF ON
Device is in Sleep mode Output is OFF,Watchdog is alive. Watchdog has timed out and the device is in Failsafe Mode. RST and WAKE must be transitioned to logic 0 simultaneously to bring the device out of the Failsafe mode. Device in Normal Operating mode
0
1
No
S
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 19
Table 12. Fail-Safe Operation and Transitions to Other 33982 Modes
0 1 Yes ON Watchdog has timed out and the device is in Failsafe Mode. RST and WAKE must be transitioned to logic 0 simultaneously to bring the device out of the Failsafe mode. Device in Normal Operating mode Watchdog has timed out and the device is in Failsafe Mode. RST and WAKE must be transitioned to logic 0 simultaneously to bring the device out of the Failsafe mode.
When experiencing a fault, the output shutdown to protect itself from damage. A fault bit is then loaded into the status register and cleared after it is read. For the output, an over-temperature condition will result in the output turning OFF until the temperature falls below the TLIM(hyst). This cycle will continue indefinitely until action is taken by the master to shut the output OFF or until the offending load is removed. Over-voltage Fault The SPSS shutdown the output during an over-voltage condition on the VPWR pin. The output remains in the OFF state, until the over-voltage condition is removed. Fault status for the output is latched into the status register. Open Load Fault The SPSS incorporates open load detection circuitry on the output. Output Open Load Fault is detected and reported as a fault condition when the output is disabled (OFF). The open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. If the open load fault is removed, the status register will be cleared after reading the register. Over-current Fault : The device has eight programmable over-current low detection levels and two programmable over-current high detection levels for maximum device protection as shown in Figure 3 , the two selectable, overriding over-current detection levels, defined by IOCH0 and IOCH1. There are also eight different over-current low detect levels (IOCL0, IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, & IOCL7) as shown in Figure 4. Any one of the IOCLx can be selected by the user, to determine a load current that, if exceeded for one of four selectable periods of time (tOCL0, tOCL1, tOCL2, tOCL3), will then latch the output off. If the load current level ever reaches the selected over current low detect level, then the device will latch off if still current limited after a period of time (tOCLx). If, at any time, the current reaches the selected IOCH level, then the device will latch off immediately, regardless of the selected tOCLx. Reverse Battery The output survives the application of reverse voltage as low as -16V. Under these conditions, the output will enhance to keep the junction temperature less than 150C and the ON resistance of the Output will fairly be the same than in normal mode. No additional passive component are required Ground Disconnect Protection In the event that the SPSS ground is disconnected from load ground, the device protects itself and safely turn off the output, regardless of the state of the output at the time of disconnection.
1 1
1 1
No Yes
S ON
x = Don't care S = State determined by SPI and /or Direct Input configurations Assumptions: Normal operating voltage and junction temperatures with FSI pin floating
Default or Sleep Mode The default mode of the SPSS is also the Sleep mode. This is the state of the device after first applying battery voltage (VPWR), prior to any I/O transitions. This is also the state of the device when the WAKE and RST are both logic [0]. In the Sleep mode, the output, and all unused internal circuitry, such as the internal 5V regulator, are off to minimize current draw. In addition, all SPI configurable features of the device are as if set to logic [0]. The device will transition to the normal or failsafe operating modes based on the Wake and Reset inputs as defined in Table 12. Fault logic what happen during failsafe
This device indicates the faults below as they occur by driving the FS pin to [0]: * Over temperature fault * Open load fault * Over current fault (high and low) * Over voltage and under Voltage fault Some of the faults are latched (see Table 9) The FS pin will return to [1] when the fault condition is removed. Specific fault information is retained in the fault register and is available via the SO pin during the first valid SPI communication after the STATR D[3:0] bits are configured to 0000. Over Temperature Fault Requirements The 33982 device incorporates over temperature detection and shutdown circuitry in the output structure. Over temperature detection occurs when the output is in the ON state.
33982 20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Under-voltage Shutdown The output latches off at some battery voltage between 5.0V and 6.0V. As long as the VDD level stays within the normal specified range, the internal logic states within the device will be sustained. This ensures that when the battery level then returns above 6.0V, the device can be returned to the state that it was in prior to the low VPWR excursion. Once the output latches off, the device must be turned off and then on again to re-enable the output.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 21
33982 22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
PACKAGE DIMENSIONS
FC SUFFIX PLASTIC PACKAGE CASE 1402-01 PQFN ISSUE A
12
12 1 2X
A M 0.1 C
PIN 1 INDEX AREA
12
15
16
M
B
2X
0.1 C G 0.1 C 2.2 2.20 2.0 1.95 0.47 0.33 0.1 M C A B
M
0.05 C
4
10X
0.05 0.00 DETAIL G
C
VIEW ROTATED 90 CLOCKWISE
SEATING PLANE
2X
0.82 0.68 0.1 0.05 0.95 0.75
0.05
M M
C
9X
CAB C
1
0.9
9X
0.1 M C A B 4.95 4.65
1.075 1.90 1.65
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. COPLANARITY APPLIES TO LEADS AND CORNER LEADS.
12
6X
6X
2.45 2.15 0.1 A B C
13
3.55 0.1 A B C 5.45 5.15 1.35 4X 1.15
16 14
1.85 (2)
6X
0.7 0.5 1.18 0.98
10X (0.25) 2X
15
2.1 1.8
(0.75)
10X
(0.4)
10X
(0.5) (0.5)
2X
0.1 A B C
10.65 10.35 0.1 A B C 11.15 10.85 0.1 A B C VIEW M-M
6 PLACES
0.15 0.05
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33982 23
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HOW TO REACH US: USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T., Hong Kong. 852-26668334 TECHNICAL INFORMATION CENTER: 1-800-521-6274
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